This invention generally relates to a method of fabricating a semiconductor memory device. More particularly, this invention relates to a method for incorporating a P-type metal electrode into a trench capacitor suitable for use in high-density integrated circuits.
Embedded memory devices fabricated within deep trench capacitors and/or vertical transistor cells have great benefits over planar-stacked device structures. Trench capacitors have replaced the planar storage capacitor in order to meet the scaling demands for high performance DRAM (dynamic random access memory) cell production.
A trench capacitor is a three dimensional device formed by etching a trench into a semiconductor substrate. After trench etching, a buried plate electrode is formed about the exterior portion of the trench and a node dielectric is then formed on the inner walls of the trench. The trench is then filled, for example, with N-type polycrystalline silicon (“N-type Poly-Si”). In order to obtain sufficient capacitance, a dopant level of about 1019 atoms/cm3 is commonly utilized. The doped Poly-Si serves as one electrode of the capacitor, often referred to as the upper electrode or storage node. An N-type doped region surrounds the lower portion of the trench, serving as the second electrode and is referred to as the lower electrode or a “buried plate” or “diffusion plate”. A node dielectric separates the buried plate and the upper electrode and serves as the insulating layer of the capacitor.
Currently, trench capacitors are formed within an integrated circuit by filling the previously formed trench with appropriately doped poly-Si. A common method for depositing poly-Si, for the upper electrode, is by chemical vapor deposition. A significant disadvantage associated with this prior method is that the poly-Si upper electrode has a relatively high electrical resistivity as compared to elemental metals. The high electrical resistivity of the poly-Si material, as the top electrode, accordingly limits the speed of the resulting device. Other disadvantages associated with the use of doped poly-Si, as an upper electrode material, include, for example, leakage due to parasitic transistors and gate depletion effects. Both of these phenomenon decrease the capacitance of the device.
One approach for overcoming the disadvantages associated with poly-Si electrodes is utilizing a metal conductor as the upper electrode, however, there are very few materials which can withstand the high thermal processing temperatures upward of 1000° C. required of deep trench capacitor/transistor structures without degrading of the node dielectric's integrity.